In the operation of electronic circuits, the peripheral circuits on an IC chip are frequently turned on before the core circuits. In the absence of a protection circuit, the peripheral circuits can be damaged by an excessive voltage when no bias voltage is first applied. A power-on bias circuit is therefore used to first bias the peripheral circuits into a high resistance condition prior to being turned on.
A conventional power-on bias circuit may be formed by connecting a number of inverters in series. One of such power-on bias circuit is shown in FIG. 1. A conventional power-on bias circuit 2 may be constructed by four inverters 12, 18, 24 and 30. An input terminal 14 of the inverter 12 is electrically connected to the input terminal 4 of the core circuit. An output terminal 10 of the inverter 30 functions as the output terminal of the power-on bias circuit 2. An output terminal 22 of the inverter 18 is electrically connected to the input terminal 26 of the inverter 24. The output terminal 28 of the inverter 24 is electrically connected to the input terminal 20 of the inverter 18, thus forming a feed-back circuit.
Referring now to FIG. 2 wherein a circuit diagram for the power-on bias circuit 2 of FIG. 1 is shown. As shown in FIG. 2, inverter 12 is constructed by a P-type transistor 34 and an N-type transistor 44. The substrate 42 and the source region 38 of the P-type transistor 34 are electrically connected to an input terminal 6 of the input/output terminal. The substrate 52 and the source region 50 of the N-type transistor 44 are electrically connected to ground 8. The gate 36 of the P-type transistor 34 and the gate 46 of the n-type transistor 44 are electrically connected to the input terminal 14 of the inverter 12. The drain region 40 of the P-type transistor 34 and the drain region 48 of the N-type transistor 44 are electrically connected to the output terminal 16 of the inverter 12.
The inverter 30 is constructed by the P-type transistor 94 and the N-type transistor 104. The substrate 102 and the source region 98 of the P-type transistor 94 are electrically connected to the input terminal 6 of the input/output terminal. The substrate 112 and the source region 110 of the N-type transistor 104 are electrically connected to ground 8. The gate 96 of the P-type transistor 94 and the gate 106 of the N-type transistor 104 are connected to the input terminal 32 of the inverter 30. The drain region 100 of the P-type transistor 94 and the drain region 108 of the N-type transistor 104 are electrically connected to the output terminal 10 of the inverter 30.
The inverter 18 and the inverter 24 forms a feedback loop. The substrate 62 and the source region 58 of the P-type transistor 54 in inverter 18 and the source region 78, the substrate 82 of the P-type transistor 74 in inverter 24 are electrically connected to the input terminal 6 of the input/output terminal. The substrate 72 and source region 70 of N-type transistor 64 in inverter 18 and the substrate 92, source region 90 of the N-type transistor 84 in inverter 24 are electrically connected to ground 8. Furthermore, the gate 56 of the P-type transistor 54 and the gate 66 of the N-type transistor 64 are electrically connected to the input terminal 20 of the inverter 18. The input terminal 20 of inverter 18 and the output terminal 16 of inverter 12 are connected to the output terminal 28 of inverter 24.
Moreover, the gate 76 of the P-type transistor 74 and the gate 86 of the N-type transistor 84 are electrically connected to the input terminal 26 of the inverter 24. The input terminal 26 of the inverter 24 is electrically connected to the input terminal 32 of the inverter 30 and the output terminal 22 of the inverter 18. The output terminal 22 of the inverter 18 is formed by electrically connecting the drain region 60 of the P-type transistor 54 and the drain region 68 of the N-type transistor 64 together. The output terminal 28 of inverter 24 is formed by electrically connecting the drain region 80 of the P-type transistor 74 and the drain region 88 of the N-type transistor 84 together.
In the operation of the power-on bias circuit 2, a high potential voltage signal is inputted into the input terminal 6 of the input/output terminal of the peripheral circuit. A voltage applied to the voltage input terminal 4 of the core circuit is determined by whether the core circuit is turned on. For instance, when the core circuit is not turned on, the voltage at the input terminal 4 is at a low potential. When the core circuit is turned on, the voltage at the voltage input terminal 4 is at a high potential.
Since inverter 18 and inverter 24 form a feedback circuit, the power-on bias circuit 2 presents a hysteresis characteristic. However, since inverter 18 and inverter 24 interfere with each other, the hysteresis characteristic of the power-on bias circuit 2 is poor such that the anti-noise capability of the circuit is poor. Furthermore, since the voltage potential at the input terminal 6 of the input/output terminal is maintained at a high potential, the leakage current that flows through inverter 12 is not reduced. The power consumption of the power-on bias circuit 2 is likewise not reduced.
It appears that while a smaller leakage current is present in a power-on bias circuit formed by inverters connected in series, the anti-noise capability of the power-on bias circuit is poor. In another conventional power-on bias circuit utilizing an inverter feedback circuit and two inverters connected in series, while the anti-noise capability is improved due to the hysteresis characteristics, the leakage current become larger which leads to higher power consumption.
It is therefore an object of the present invention to provide a power-on bias circuit that is capable of producing a smaller leakage current and improved hysteresis characteristics.
It is another object of the present invention to provide a power-on bias circuit that does not have the drawbacks or shortcomings of the conventional power-on bias circuit.
It is a further object of the present invention to provide a method for operating a power-on bias circuit by incorporating a Schmitt trigger circuit such that the hysteresis window of the circuit is enlarged to improve the anti-noise capability and to reduce the leakage current.